DESIGN OF A CLOCK DISTRIBUTION NETWORK USING LOW POWER PRESCALER AND FUSED P & S COUNTERS
Abstract
- In this paper we have shown the design of clock distribution network using 2/3 prescaler. In wireless communication applications like WLAN, ZIGBEE, Bluetooth etc. frequency synthesizer is the major component. The speed of the frequency synthesizer depends on the pre-scaler and the voltage-controlled oscillator. 2/3 The pre-scaler must be implemented using either TSPC (true single-phase clock) or ETSPC (extended true single-phase clock) and triggers. Instead of using an AND gate and an OR gate, this article recommends embedding two NOR gates in two stages of the pre-scaler design. The two designs are compared in terms of power consumption. Using the recommended pre-range meter, we designed a clock distribution network that divides the clock distribution network by 2,3,4,5,32,33, 47, 48, and up to 5Ghz. The system is also centrally used for combining programmable design counters and swallowing counters. Clock allocation network system code is written in validation and modeled using Xilinx and Modelsim.
Key Words: TSPC, ETSPC, Frequency Synthesizer, Prescaler, clock distribution.
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